Quick Solutions to Solve SPICE Convergence Issues.

This article focuses on PSPICE, but most of the parameters and their settings are common to other SPICE versions like XSPICE NGSPICE IsSPICE HSPICE.

The SPICE simulation convergence issues mainly occur for 3 types of problems:

Circuit Topology Errors

these types of errors are often signaled with precise messages from the SPICE simulation software and it is easy to identify and correct them.

SPICE simulator Options Settings

for example, in the transient analysis, it ‘s necessary to consider the right timestep for the working frequency of the device, and in some cases we have to settle for moderate accuracy, because tighter the accuracy become and more likely we can find convergence errors.

Unrealistic SPICE models

convergence problems can arise from SPICE models with strong non-linearities and discontinuities.

Now let’s see what are the quick solutions to solve the most common convergence issues due to these different types of problems.

Circuit Topology Errors

Missing ground, error message: Node is floating.

The SPICE algorithm calculates the voltage of each point of the circuit with respect to a reference point,
this reference point is precisely the ground which must necessarily be present in the circuit.
It ‘s enough to add the ground reference wherever we wish.

Missing DC path to ground, error message: Node is floating.

For the reasons explained in the previous case, it is necessary to check that no point of the circuit is isolated
from the ground reference. If we want to “simulate” an isolation of a node from the ground, we do it placing a
very high value resistor, which actually maintains the continuity with the ground reference.
Check that the node has a direct connection with the ground reference.

Unmodeled pins, error message: Less than two connections at node

this error occurs when there is no PSpice model attached to the Capture part or when there’s a
wire “floating”, that is connected to a device pin without connection to another pin.

Avoid loops containing voltage sources or inductor, error message: voltage source or inductor loop

We can add a small series resistance.

Avoid series cpacitors o current sources

verify that there are no series capacitors or series current sources.

Convergence Problems due to SPICE Simulation options settings

First of all it is necessary to set the timestep appropriately for the device we are simulating. For example, if we want to simulate an oscillator at 1 khz, with a period of T=1ms, we ‘ll have to set a timestep of the order of T/10 or lower, to have a decent resolution of the simulation.
Let’ s distinguish the solutions that can be adopted in the two main types of analysis, DC and Transient.
Once DC convergence is achieved the AC analysis will also converge.

SPICE DC convergence solutions

ITL1: set ITL1=500, this set iterations limit that SPICE will perform for DC and bias.

ITL2: set ITL2=500, this set iterations limit that SPICE will perform for DC and bias before giving up.

ITL6: set ITL6=100 (Advanced Options), this increases Source stepping iteration limit, Default value
is 0, which disables source stepping.

reduce ABSTOL Absolute current tolerance, it should be set to about 8 orders of magnitude below the level of maximum current,
the dafault value is 1pA

Reduce VNTOL Absolute voltage tolerance, as for ABSTOL it should be set to about 8 orders of magnitude below the level of maximum voltage, the default value is 1uV

Reduce RELTOL this is the relative error allowed for node voltage and branch current. Set RELTOL= 0.01 to reach a compromise between accuracy and simulation run time. The default value is 0.001.

GMIN set GMIN = 1n or 0,1n. GMIN is the minimum conductance across all semiconductor devices

GMINSTEPS (Advanced Options) set GMINSTEPS=200 . this option adjusts the number of increments for GMIN
during the DC analysis.

Change DC Power supplies into Pulse generator

NODESETs use .NODESETs statement to assign a voltage to a node. This can be done for example when the node-voltage table shows unrealistic voltages. If it’s not available a proper estimation of the node DC voltage, use
a .NODESET of 0V.

SPICE Transient Convergence solutions

RELTOL also for the transient analysis Set RELTOL= 0.01 (The default value is 0.001), that decreases the accuracy
of the simulation by increasing the error tolerance required for convergence.

ITL4 set ITL4=2000 , this increases the number of iterations before a nonconvergence warning is issued

reduce ABSTOL Absolute current tolerance, it should be set to about 8 orders of magnitude below the level of maximum current, the dafault value is 1pA

Reduce VNTOL Absolute voltage tolerance, as for ABSTOL it should be set to about 8 orders of magnitude below the level of maximum voltage, the default value is 1uV

ITL5 set ITL5=0 that assigns infinity to the total transient iteration limit.

Reduce rise and fall of PULSE sources

GEAR (Advanced Options) Select METHOD=GEAR, this is the integration method that SPICE uses to solve transient equations. Very useful for oscillators and switching circuits SPICE simulations.

TRTOL set TRTOL=40. this is the tolerance for integration error calculated using transient analysis. The TRTOL
value should NOT be greater than 1/RELTOL. the default value is 7.

IC set Initial conditions for the capacitors at their expected operating voltage. Setting this data causes
SPICE to bypass the DC operating point analysis.

Use reliable SPICE models.

As we know The SPICE models do not coincide with the devices they model, but represent only a partial description of them. SPICE models with strong discontinuities or non-linearities can create serious convergence problems.
These discontinuities can originate from the omission of certain device behaviors, such as element parasitics,
capacitance for all semiconductor junctions, stray capacitance, RC snubbers around diodes.
In most cases we can rely on the SPICE models released by vendors, if instead we model the device directly, we have to smooth as much as possible any cause of discontinuities and nonlinearities.

Reference:

EMA Design Automation Resolving Simulation Errors
SPICE Circuit Handbook Steven. M Sandler Charles Hymowitz

Circuit-Breaker Model for Over-Current Protection Simulation of DC Distribution Systems.

T. ROBBINS
TELSTRA RESEARCH LABORATORIES
BOX 249 ROSEBANK MDC, CLAYTON VICTORIA 3168, AUSTRALIA
Email: t.robbins@trl.oz.au

Abstract: This article describes an electrical model of a thermalmagnetic circuit-breaker that can accurately simulate characteristic behaviour over a wide range of overcurrents, including operation in the magnetic region. The model has been validated against measured waveforms from both a high-current DC test facility and a distributed power system rack. The circuit-breaker model can be coupled with other distribution component models to simulate the protection performance in telecommunications DC distribution systems.

1.Introduction

The performance of protection, distribution and storage devices significantly affects both the reliability and safety of the DC power system. Voltage excursions caused by an over-current instance can cause electronic equipment to malfunction due to over-voltage, and disrupt service due to under-voltage. Poor discrimination between protection devices can cause upstream device operation, resulting in major interruption to service. The rapid advancement of both computing power and analogue circuit simulation programs derived from SPICE software provides a relatively user-friendly environment for over-current protection design and analysis. This is advantageous as telecommunications power distribution systems are often large and complex, and developing an equivalent circuit model for a power system is not a trivial task.

The circuit-breaker model described in this article implements the enhanced modelling functions available with PSpice’s Analog Behavioural Modelling to include circuit-breaker current, time and arcing dependent characteristics. This model complements and extends previously published modelling work [1-2] by Telstra Research Laboratories on other power system components.

2.Circuit-Breaker Characteristic Operation

A typical thermal-magnetic circuit-breaker operates (trips) in two distinct modes; the thermal mode occurs for device currents from 1 up to about 10-15 times the rated setting current, and the magnetic mode occurs for all current levels above the thermal operating region. Characteristic current-time curves for the device operating in the thermal region can be approximated by an equation where i n t equals a constant, whereas in the magnetic region the operating time (typically <20ms) is not well defined in device data curves and specifications, as test circuits are based on rectified AC power sources which have typical rise times exceeding a few milliseconds.

The circuit-breaker model presented in this paper has been developed for a 125A moulded device (10kA fault rating), which is commonly used to protect individual battery strings within Telstra’s distributed power supplies.

For device operation in the thermal region, the characteristic i n t form of the current-time curve can be obtained from the device specification curve as shown in Figure 1. A value of n = 3.5 gives an adequate fit over the range of currents within the thermal operating region.

Fig.1 125A circuit-breaker current-time operating
boundary curves (courtesy of GEC ALSTHOM
AUSTRALIA).

For device operation in the magnetic region, characteristic current-arc voltage-time behaviour has been observed for the circuit-breakers operating in a high-current DC test facility over a range of current levels and circuit time constants. At the start of such a fault instance, the current passing through the closed circuit-breaker contacts increases to a level where magnetic activation forces the contacts to open. As the contacts start to open an arc is developed which is inherently unstable and a complex voltage-current characteristic occurs as the arc progresses through to extinction.
For the 125A circuit-breaker operating in the magnetic region, the contacts are forced open when the current level typically rises above 2-4kA. Circuit-breaker operation was measured over a range of circuit conditions, such as:

· fast rates of current rise exceeding 10kA/ms, which resulted in short pre-arcing times of about 0.15- 0.2ms (eg. results from a test circuit with 5.4kA prospective current and 0.26ms time constant are shown in Figure 2).

· high prospective current levels exceeding 10kA, which result in pre-arcing times around 0.9ms for circuit time constants of about 1.2ms, as shown in Figure 3. It should be noted that special oscilloscope probing and current shunt techniques are required to record clean waveforms in the high transient noise environment that occurs in a high current test facility.

Fig.2 Measured current and voltage waveforms for
a 125A circuit-breaker operating in 54VDC test circuit
with 5.2kA prospective current and 0.25ms prospective
time constant; 1kA/div current, 20V/div voltage and
0.5ms/div.

Fig. 3 Measured current and voltage waveforms for
a 125A circuit-breaker operating in 54VDC test circuit
with about 12kA prospective current and about 1ms
prospective time constant; 1kA/div current, 50V/div
voltage and 0.5ms/div.

Pages: 1 2 3

Fuse Model For Over-Current Protection Simulation of DC Distribution Systems.

T. Robbins
Telecom Australia Research Laboratories
770 Blackburn Road, Clayton, 3168
Australia

Abstract: The design and analysis of over-current protection for telecommunication DC power systems can be greatly assisted by the use of a computer-aided simulation tool. This article reports on the development of a fuse model for SPICE derived software that can accurately represent characteristic fuse parameters. The fuse model can also be adapted to represent the operation of circuit breakers.

1.Introduction

The design and analysis of over-current protection for telecommunication DC power systems can be greatly assisted by the use of a computer-aided simulation tool. However, a simulation is only as accurate as the component models and element values used to represent the real world. This article reports on the development of a fuse model that can accurately represent fuse characteristics. The fuse model can also be adapted to represent the operation of circuit breakers.
The performance of over-current protection devices significantly affects both the reliability and safety of the DC power system. Voltage excursions resulting from the operation of a fuse during a short circuit can cause electronic equipment malfunction due to over-voltage, and disrupt service due to under-voltage. Poor discrimination between protection devices can cause upstream device operation, resulting in major interruption to service.

The rapid advancement of both computing power and analogue circuit simulation programs derived from SPICE software provide a user-friendly environment for over-current protection design and analysis. This environment is advantageous as telecommunications power distribution systems are often large and complex, and developing an equivalent circuit model for apower system is not a trivial task.

The analysis of DC distribution systems using computer simulation has been shown to provide fair agreement between simulated and experimental results [1,2,3]. However, the fuse models developed have not been able to accurately represent fuse characteristics. Typical parameters for a fuse operating in a circuit with a given time constant and prospective current are rated current ir, peak current ip, pre-arcing time tp, arcing time ta, total operating time tt= tp + ta, pre-arcing i²t (i²t)p, arcing i²t (i²t)a and total operating i²t (i²t)t= (i²t)p + (i²t)a. Figure 1 illustrates some of these parameters. The prospective current for a circuit is the maximum current that would be reached if the fuse did not operate.

The i²t or current-squared time rating is a commonly used fuse characteristic when operating current levels are much higher that the rated fuse current ir. The circuit time constant defines the ratio L/R, where L and R are the effective circuit inductance and resistance components in series with the fuse and energy source.

Fig 1. Typycal fuse parameters

A fuse model is developed in Section 2 and model validation is undertaken in Section 3. Section 4 discusses the development of other DC power system component models for application to the analysis of over-current protection, and the paper is summarised in Section 5.

Pages: 1 2 3 4

SPICE simulation of a Combo Wave Generator.

Thanks for this article to ssleandro

In this article we ‘ll se how to implement a template for a Combination Wave Generator that can be a Surge Generator, a Line Impedance Stabilization Networks (LISN), motor control, ripple current, etc. This model can be very useful for hardware engineers which can utilize it in their projects to speed up project development. The platform used for the simulation is PSpice but
it can easily replicated in other SPICE simulation software.

The simplified model of the GPM consists of an High-Voltage source U, a charging resistor Rc, an energy storage capacitor Cc. This part of circuit is connected by a switch to 2 Pulse duration shaping resistors Rs, an impedance matching resistor Rm and a Rise time shaping indutor Lr, as in the picture below

typical values of this components are: Cc=7.76μF, Rs1=14.8 Ohm, Rm=1.05 Ohm, Lr=9.74μH, Rs2=23.3 Ohm. The peak voltage on Rs2 can be 1KV, 2KV,..6KV.

In the following schematic we set the high voltage with the initial condition of the CapacitorCc, for example for 6KV, we set 6300 in the PSpice IC field of the Cc component. We can adjust the time in U1 to make surge hit at 90/270 degree or whatever phase we want.

Calibration of Surge Generator.

The IEC/EN 61000-4-5 standars requires the following waveform of open-circuit voltage with no Coupling/Decoupling network (CDN) connected

This is the result of the simulation that shows a voltage waveform that fullfills requirementof IEC/EN 61000-4-5

Below the image of the waveform of short-circuit current with no CDN connected

and here again the simulated results:

Ipeak is about 1.5KA, T1 is 8uS and T2 is 20uS. The effective coupling impedance is 2Ohm. The simulated current waveform fulfills requirement of IEC/EN 61000-4-5 standards.

Pages: 1 2

Importing SUBCKT PSpice Netlist into TINA

In this tutorial we consider the SPICE netlists using a SUBCKT subcircuit statement . The syntax of all the primitives, resistors, capacitors, inductors, is the same for TINA and PSpice.

For more complex models, it is possible that some PSpice netlists may contain formats not compatible with TINA. This article expalins a procedure that shows how to import a PSpice netlist, verify its syntax and make a TINA macromodel.

Below the schematic of a speech band amplifier from TINA Designsoft collection circuits. It’s implemented with two opa345 operational amplifiers

Speechbandamplifier

We want to replace the SPICE model of the opa345 with the following opa347 PSpice netlist, with SUBCKT statement

rename the .txt file as opa347.cir, then from the menu File, choose Import, PSpice Netlist (.CIR)

Select opa347.cir file, the Netlist Editor window opens

Click on “Compile” icon to verify the compatibility of SPICE statements with TINA, if there are no compatibility issues a “Succesfully completed” message appears

Close the Netlist Editor window and select “New Macro Wizard..” from Tools menu

The New Macro Wizard window appears, enter opa347 as name, uncheck “Current circuit”. Now it’ s possible select the file opa347.cir with a directory window. Uncheck “Auto-generated”

Now click the “Shape” ellipsis and choose a graphic symbol from the list. If there are no symbols that fit our model, we can leave the check in the “Auto-generated” box

Save the macro (.TSM file) for example in the Macrolib directory

Pages: 1 2

From the Capture schematic to the PCB layout

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Pages: 1 2 3 4 5 6 7

Circuit Topology Errors

SPICE simulator Options Settings

Unrealistic SPICE models

Circuit Topology Errors

Convergence Problems due to SPICE Simulation options settings

Use reliable SPICE models.

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