Single Channel 4 bit Pulse Code Modulation Transmitter

(9 customer reviews)

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e74609d6-20c1-40a0-8115-fcf0c1da02e4.rar

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Description

SPICE simulation of a PCM system that uses 4 of the 8 bits available. The input signal is a 1Khz sinusoidal sampled at 8khz, which is the rate used in the public switched telephone network (PSTN), and the ADC parallel output it’s converted to a serial bit stream. To show the recovered signal, a serial to parallel converter and a DAC is attached to the transmitter. The DAC output is low pass filtered.

  • Digital Analog mixed analysis input signal, output of DAC and recovered signal FFT of recovered signal

9 reviews for Single Channel 4 bit Pulse Code Modulation Transmitter

  1. ahmed4fcb

    tnx what an excellent project

  2. Chrishew09

    where can i find the model for the 74116? it’s not part of the eval.lib file

  3. tobytone

    No, you are right, it’s not but, ok, here it is:
    * 74116 DUAL 4-BIT LATCHES WITH CLEAR
    *
    * The TTL Data Book, Vol 2, 1985, TI
    * MCG 07/09/93
    *
    .SUBCKT 74116 C1BAR_I C2BAR_I CLRBAR_I D1_I D2_I D3_I D4_I Q1 Q2 Q3 Q4
    + optional: DPWR=$G_DPWR DGND=$G_DGND
    + PARAMS: MNTYMXDLY=0 IO_LEVEL=0
    *
    U116_1 BUFA(7) DPWR DGND
    + D1_I D2_I D3_I D4_I C1BAR_I C2BAR_I CLRBAR_I
    + D1 D2 D3 D4 C1BAR C2BAR CLRBAR
    + D0_GATE IO_STD
    *
    U116_2 DLTCH(4)
    + DPWR DGND
    + $D_HI CLRBAR LAT
    + D1 D2 D3 D4
    + Q1 Q2 Q3 Q4
    + $D_NC $D_NC $D_NC $D_NC
    + D_74116 IO_STD
    *
    U116_3 INVA(2)
    + DPWR DGND
    + C1BAR C2BAR
    + C1 C2
    + D0_GATE IO_STD
    *
    U116_4 AND(2)
    + DPWR DGND
    + C1 C2
    + LAT
    + D0_GATE IO_STD
    *
    U116CON CONSTRAINT(7) DPWR DGND
    + CLRBAR C1BAR C2BAR D1 D2 D3 D4
    + IO_STD
    +
    + WIDTH:
    + NODE = CLRBAR
    + MIN_LO = 18NS
    + MIN_HI = 18NS
    +
    + WIDTH:
    + NODE = C1BAR
    + MIN_LO = 18NS
    + MIN_HI = 18NS
    +
    + WIDTH:
    + NODE = C2BAR
    + MIN_LO = 18NS
    + MIN_HI = 18NS
    +
    + SETUP_HOLD:
    + DATA(4) D1 D2 D3 D4
    + CLOCK LH = C1BAR
    + SETUPTIME_HI = 8NS
    + SETUPTIME_LO = 14NS
    + RELEASETIME = 2NS
    + HOLDTIME = 8NS
    +
    + SETUP_HOLD:
    + DATA(4) D1 D2 D3 D4
    + CLOCK LH = C2BAR
    + SETUPTIME_HI = 8NS
    + SETUPTIME_LO = 14NS
    + RELEASETIME = 2NS
    + HOLDTIME = 8NS
    +
    + SETUP_HOLD:
    + DATA(1) C1BAR
    + CLOCK LH = CLRBAR
    + SETUPTIME = 8NS
    *
    .ENDS

  4. tobytone

    If you can’t use this because of the formatting, email me and I’ll send you the complete file!

  5. Chrishew09

    Please forgive me, but I do not see any way to email you directly through youspice.

  6. tobytone

    ok, leave your email and I’ll get back to you.

  7. sandeepreddy

    hiiii good project and is it works as hard ware project ?

  8. Paul Tobin

    Hello, I have not built this circuit but I see no reason why you couldn’t build it in hardware.
    Paul Tobin

  9. sandeepreddy

    ok can you provide me documentation of the project so that i can CLEARLY KNOW THE WORKING OF THE CIRCUIT? CAN YOU MAIL ME

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