Parallel In Serial Out Shift register

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b03e2f84-2637-47d7-8675-2edee1f8bed9.zip

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Description

the circuit is implemented with D flip-flops and nand gates. D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least significant bit. when the shift/write line is low, the data is written, when the line is high, the data is shifted. The register performs right shift operation on the application of a clock pulse.

  • : Free
  • : Simple
  • : 11-20
  • : PSpice
  • : 16.5+
  • : No

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