Edge triggered D Flip Flop

Rated 5.00 out of 5 based on 1 customer rating
(1 customer review)

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94d2f48c-2e5f-400f-94fe-465778aa4613.rar

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Description

SPICE simulation of an edge triggered D flip flop implemented with two level-sensitive latches in cascade. When the clock goes high, the output “follows” the input. The value of output Q can’t change its state until next rising front of clock.

  • : Free
  • : Intermediate
  • : 11-20
  • : LTspice
  • : IV
  • : No

1 review for Edge triggered D Flip Flop

  1. Rated 5 out of 5

    asasfaf

    you can not make CMOS d flip flop on Spice without going to internet and finding out this circuit. very helpful.

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