DPLL circuit for 1 Gbit/s clock recovery

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2042a32d-e691-411a-b7c8-b2ae425860b1.zip

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Description

SPICE simulation of 1 Gbit/s clock recovery circuit using a NRZ (Non Return to Zero) data format. The Digital Phase Locked Loops used for clock recovery uses a Hogge phase detector and a VCDL (Voltage Controlled Delay Line), the output of which is fed back to get a positive feedback for sustaining the oscillation.

  • : Free
  • : Advanced
  • : >100
  • : LTspice
  • : IV
  • : No

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