Delay-Locked Loop (DLL) SPICE simulation

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Problems with PLL output jitter resulting from the VCO output frequency changing with a constant input voltage (VjnVC0 = constant) has led to the concept of a delay-locked loop (DLL). Assuming that a reference clock is available at exactly the correct frequency, the input data is delayed through a voltage-controlled delay line (VCDL) a time t0 until it is synchronized with the reference clock. Jitter is reduced by using an element, the VCDL, that does not generate a signal (like the VCO does). The transfer function Fclock/Fout is zero (the phase of the reference clock is taken as the reference for the other signals in the DLL, i.e., Fclock = 0), so that oscillator noise and the resulting jitter are not factors in DLL design.


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