SPICE simulation of an 8 stage voltage controlled delay line. The VCDL is used to provide delay in a delay locked loop (DLL). This schematic has eight delay cells. The differential inputs were generated using an inverter and a transmission gate. The outputs are evenly spaced and they only swing up to Vref = 500mV. This is done to minimize the effects of power supply and ground noise on the delay of the circuit.
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