Capacitance Multiplier

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Description

A capacitance multiplier circuit is implemented with an operational amplifier opa725. The effective value of a small capacitor C1 is increased to a much larger value, The capacitance seen at Vout is: Cout = C1 * R1/R3. For C1=100pF, the resulting capacitance is 100nF. The output capacitance can be verified with the cutoff frequency of resulting R-C circuit, Fc= 1/(6.28*R*C) =1.59 Hz.

  • cutoff frequency

2 reviews for Capacitance Multiplier

  1. paulcardno

    Hey TINADesign Thanks for this design. Just starting to understand cap multiplier and your design is interesting, thanks for that. Questions.1) there appear to be two R3 resistors, I assume that the top R3 resistor between opamp negative and output is actually R2. thanks again Paul

  2. TINADesigner

    Yes you are right, the name of the top R3 was mistyped. I’ve changed it to R5. Note that now you can also run this example with the on-line version of TINA called TINACloud, change the component parameters and see the effect of the changes. Best regards Michael DesignSoft

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