Home › Forums › General Electronics › Digital Basic Components › time step too small in ltspice trouble with dflop instance › Reply To: time step too small in ltspice trouble with dflop instance
July 2, 2013 at 4:15 am #16441
are you refering to the A3 AND gate in both projects? The purpose of this AND gate is to reset the D flipflop when both of them have their Q output set to 1. And then to prevent from having the state where QB=QH=1. This topology is found in the litterature (projet.asc) and works on ORCAD PSPICE.