# Quick Solutions to Solve SPICE Convergence Issues.

This article focuses on PSPICE, but most of the parameters and their settings  are common to other SPICE versions like XSPICE NGSPICE IsSPICE HSPICE.

The SPICE simulation convergence issues mainly occur for 3 types of problems:

• #### Circuit Topology Errors

these types of errors are often signaled with precise messages from the SPICE simulation software and it is easy to identify and correct them.

• #### SPICE simulator Options Settings

for example, in the transient analysis, it ‘s necessary to consider the right timestep for the working frequency of the device, and in some cases we have to settle for moderate accuracy,  because tighter the accuracy become and more likely we can find convergence errors.

• #### Unrealistic SPICE models

convergence problems can arise from SPICE models with strong non-linearities and discontinuities.

Now let’s see what are the quick solutions to solve the most common convergence issues due to these different types of problems.

## Circuit Topology Errors

Missing ground, error message: Node is floating.

The SPICE algorithm calculates the voltage of each point of the circuit with respect to a reference point,
this reference point is precisely the ground which must necessarily be present in the circuit.
It ‘s enough to add the ground reference wherever we wish.

Missing DC path to ground, error message: Node is floating.

For the reasons explained in the previous case, it is necessary to check that no point of the circuit is isolated
from the ground reference. If we want to “simulate” an isolation of a node from the ground, we do it placing a
very high value resistor, which actually maintains the continuity with the ground reference.
Check that the node has a direct connection with the ground reference.

Unmodeled pins, error message: Less than two connections at node

this error occurs when there is no PSpice model attached to the Capture part or when there’s a
wire “floating”, that is connected to a device pin without connection to another pin.

Avoid loops containing voltage sources or inductor, error message: voltage source or inductor loop

We can add a small series resistance.

Avoid series cpacitors o current sources

verify that there are no series capacitors or series current sources.

## Convergence Problems due to SPICE Simulation options settings

First of all it is necessary to set the timestep appropriately for the device we are simulating. For example, if we want to simulate an oscillator at 1 khz, with a period of T=1ms, we ‘ll have to set a timestep of the order of T/10 or lower, to have a decent resolution of the simulation.
Let’ s distinguish the solutions that can be adopted in the two main types of analysis, DC and Transient.
Once DC convergence is achieved the AC analysis will also converge.

SPICE DC convergence solutions

ITL1: set ITL1=500, this set iterations limit that SPICE will perform for DC and bias.

ITL2: set ITL2=500, this set iterations limit that SPICE will perform for DC and bias before giving up.

ITL6: set ITL6=100 (Advanced Options), this increases Source stepping iteration limit, Default value
is 0, which disables source stepping.

reduce ABSTOL Absolute current tolerance, it should be set to about 8 orders of magnitude below the level of maximum current,
the dafault value is 1pA

Reduce VNTOL Absolute voltage tolerance, as for ABSTOL it should be set to about 8 orders of magnitude below the level of maximum voltage, the default value is 1uV

Reduce RELTOL this is the relative error allowed for node voltage and branch current. Set RELTOL= 0.01 to reach a compromise between accuracy and simulation run time. The default value is 0.001.

GMIN set GMIN = 1n or 0,1n. GMIN is the minimum conductance across all semiconductor devices

GMINSTEPS (Advanced Options) set GMINSTEPS=200 . this option adjusts the number of increments for GMIN
during the DC analysis.

Change DC Power supplies into Pulse generator

NODESETs use .NODESETs statement to assign a voltage to a node. This can be done for example when the node-voltage table shows unrealistic voltages. If it’s not available a proper estimation of the node DC voltage, use
a .NODESET of 0V.

SPICE Transient Convergence solutions

RELTOL also for the transient analysis Set RELTOL= 0.01 (The default value is 0.001), that decreases the accuracy
of the simulation by increasing the error tolerance required for convergence.

ITL4 set ITL4=2000 , this increases the number of iterations before a nonconvergence warning is issued

reduce ABSTOL Absolute current tolerance, it should be set to about 8 orders of magnitude below the level of maximum current, the dafault value is 1pA

Reduce VNTOL Absolute voltage tolerance, as for ABSTOL it should be set to about 8 orders of magnitude below the level of maximum voltage, the default value is 1uV

ITL5 set ITL5=0 that assigns infinity to the total transient iteration limit.

Reduce rise and fall of PULSE sources

GEAR (Advanced Options) Select METHOD=GEAR, this is the integration method that SPICE uses to solve transient equations. Very useful for oscillators and switching circuits SPICE simulations.

TRTOL set TRTOL=40. this is the tolerance for integration error calculated using transient analysis. The TRTOL
value should NOT be greater than 1/RELTOL. the default value is 7.

IC set Initial conditions for the capacitors at their expected operating voltage. Setting this data causes
SPICE to bypass the DC operating point analysis.

## Use reliable SPICE models.

As we know The SPICE models do not coincide with the devices they model, but represent only a partial description of them. SPICE models with strong discontinuities or non-linearities can create serious convergence problems.
These discontinuities can originate from the omission of certain device behaviors, such as element parasitics,
capacitance for all semiconductor junctions, stray capacitance, RC snubbers around diodes.
In most cases we can rely on the SPICE models released by vendors, if instead we model the device directly, we have to smooth as much as possible any cause of discontinuities and nonlinearities.

Reference:

EMA Design Automation Resolving Simulation Errors
SPICE Circuit Handbook Steven. M Sandler Charles Hymowitz

# Creating a Spice Subcircuit (.Subckt) manually

CREATING A SPICE SUBCIRCUIT

Want to automatically create subcircuits?
The Professional edition of 5Spice 2.0 includes a sophisticated tool to make a schematic into a Spice subcircuit (.Subckt). Later you can modify the schematic and then update the subcircuit with the tool.

Creating a subcircuit manually

A subcircuit definition contains Spice circuit elements, has a name and specifies the circuit nodes that connect it to the main circuit. Creating a subcircuit allows you to reuse the circuit multiple times in a design and in future designs. Subcircuits are similar to subroutines in software programming.

Subcircuits may contain basic circuit elements, other subcircuit definitions, device models, and calls to subcircuits defined internally or externally. Spice program control lines may not appear within a subcircuit definition.

In 5Spice, subcircuits are stored in the program’s library. You may add any subcircuit to the library and link it to the schematic’s subcircuit symbol.

Caution

As useful as subcircuits are, there is little help in finding errors except to run Spice and see it fail. The syntax must be perfect as well as the circuit.

My experience is that developing very simple subcircuits is easy but developing more advanced subcircuits is slow and sometimes extremely frustrating. This is because there are no specialized tools to help find the syntax errors and bugs in a new subcircuit. It can be hard work, cryptic error messages and guessing.

Basics

• Subcircuit definitions are stored in text files. The file name may not contain the space character. In 5Spice’s Library, file extensions .DOC, .BAK, .SAV, .TXT and .HTM are not recognized as subcircuit files.
• All file lines must start in the first (left-most) column. When a line is too long to fit, break the line and use the + symbol as the first character of the extension line.
• Spice sees “SPICE” and “spice” as the same.
• Any device models or subcircuit definitions included in a subcircuit definition are strictly local (these models and definitions are not known/visible outside the subcircuit definition).
• Any circuit nodes not included on the .SUBCKT line are strictly local with one exception: Spice defines node 0 (zero) as circuit ground in both circuits and subcircuits. node 0 always connects everywhere.
• circuit nodes may be identified with either numbers or letters. examples: 1 2 In Out3
• non-English speaking countries: numbers in Spice must be written as 1.23 (not as 1,23)
• General form:

.SUBCKT  SubName Node1 Node2 Node3 …

circuit element lines

.ENDS

A subcircuit definition begins with the .SUBCKT line.

SubName is the subcircuit’s name. The name consists of letters and numbers from the English alphabet. The space character is not allowed. In 5Spice the maximum length for the name is 32 characters and the following characters may not be used in the name: ~ @ # ? . :

Node1, Node2, etc. are the external nodes. Only these nodes connect outside the subcircuit. It is their order on the .subckt line that determines their external connection, NOT their name or number! 0 (zero) is not allowed as an external node.

The circuit element lines which immediately follow the .SUBCKT line define the subcircuit. The last line in a subcircuit definition is the .ENDS line.

Example

a simple AC coupled amplifier

Draw the circuit. Number the circuit nodes 1 to 5 in any order. Ground is always node 0. Nodes 1,2,3 need to connect externally to provide power and get a signal in and out of the subcircuit.

Choose a name for the subcircuit: ACamplifier

consult Spice manual for syntax details for each type of part

 * external nodes:  in power out .SUBCKT  ACamplifier 2 1 3 R1 1 4 2K R2 4 0 500 C1 2 4 10n * transistor node  order C B E. calls model named 2N2222 Q1 3 4 5 2N2222 Rc 1 3 2K Re 5 0 1e3 .model 2N2222 NPN  (BF=50 IS=1E-13 VBF=50 and so on) .ENDS

Note: If you  have a file with two subcircuits (Sub1,Sub2) that both call a third (Sub3), you can write Sub3 as a separate subcircuit in the same file.

Example – Passing Parameters to the subcircuit

5Spice and high end Spice simulators allow a subcircuit to accept parameter values passed from the schematic or from the subcircuit call line. The following shows the previous subcircuit but with the values of R1 and C1 as parameters. The parameter syntax shown for the .SUBCKT line works with 5Spice, PSpice, IsSpice and possibly others.

.SUBCKT  ACamplifier 2 1 3 PARAMS: Cin=10n Rbias=2K

R1 1 4 {Rbias  * 1.12}

R2 4 0 500

C1 2 4 {Cin}

.ENDS ACamplifier

5Spice requires that all parameters be listed on the .SUBCKT line and given a default value. The order is not important. The parameter must be enclosed with braces {} where it is used in the subcircuit. This includes the formula for Spice’s B source. Program registration is required to enter values for these parameter from the schematic, otherwise the default values are used.

5Spice also allows defining parameters inside a subcircuit using .PARAM lines. See the program’s Help for this and for information on using parameters in equations for component values, .PARAM lines or the B source.

Important for 5Spice

When writing more complex subcircuits, see subcircuits, 5Spice compatibility with in the program’s Help index for details on the program’s Spice3 syntax extensions and PSpice syntax compatibility. This includes passing parameter values to subcircuits.

Good Practice

• start simply, get the subcircuit working, add complexity later
• add a comment line identifying the circuit function of the external nodes listed on the .SUBCKT line
• place any models and subcircuits defined within the subcircuit at the end
• add the subcircuit name to the .ends line: .ENDS MySub1
• avoid PSpice specific syntax if you want your subcircuit to work with all simulators

In schematic based simulators like 5Spice, the schematic symbol automatically calls the subcircuit linked to the symbol. If you are using traditional Spice or calling a subcircuit from another subcircuit, write the call as follows:

X Node1 Node2 Node3 … SubName

example: Xamp  5 4 2  ACamplifier

The identifier must start with the letter X. SubName is the subcircuit’s name. Node identifiers Node1, Node2, etc. are the node numbers/names in the calling circuit that connect to the subcircuit. The number of nodes on the call line must match the number listed in the .subckt line of SubName. Spice connects the nodes from the call line to the subcircuit in the order they are listed.

Note: In 5Spice, if one subcircuit calls another subcircuit, both subcircuits must be in the same file.

Calling with parameters

If the subcircuit has parameters defined, they are shown when editing the schematic symbol and new values can be assigned. When writing a call  by hand, parameter values placed in the call line override the  default values defined in the subcircuit. The parameter syntax shown works with 5Spice, PSpice, IsSpice and possibly others.

Xamp 5 4 2  ACamplifier PARAMS: Cin=20n Rbias=2.7K

<———  end of creating Spice subcircuit ———>

You may want to create a separate Library subdirectory …\Library\Subcircuits\Testing for debugging your subcircuits. Place the file containing the subcircuit there. (To find where the Library is located, go to main menu>TOOLS>Rebuild Spice model Library)

In 5Spice, go to the Tools menu and Rebuild the Library.

Place a subcircuit symbol in the schematic and double click it to edit it. In the edit window that opens, use the Search box to search for the name of your subcircuit (not the name of its file). Click the subcircuit name in the listing.

Problem on selecting

If there is a graphic image next to its name in the listing then 5Spice has found a problem in the subcircuit. If the error message is PSpice compatibility problem, see the section Important for 5Spice above. Review the subcircuit carefully for syntax problems. You can find which line the problem is on by opening the report file generated when the library is rebuilt.

report file: …\Library\IndexSub.ndx.rpt

5Spice only checks to be sure it can find models and subcircuits and for unsupported syntax and PSpice syntax compatibility. It does not syntax check every line.

Note that users make frequent syntax errors in the formulas used with the B source.

If you can’t find a problem, open the subcircuit file in a text editor (Notepad) and copy the .subckt and .ends line to make a new, empty subcircuit definition with the same name. Then rename the original subcircuit (add “x” on end of name) and save the file. Rebuild the Library again (will be no errors in the empty definition). Finally restore the name of your original subcircuit, comment out the empty one and save the file. The program will now let you select and load the subcircuit so you can see what error messages WinSpice (the Spice simulation engine) produces.

selection OK

When the subcircuit has been selected, draw the test schematic – something very simple for DC Bias. Run the DC Bias analysis. If things work, great. Do some checking that the subcircuit functions as you expect. Remember that a 1M resistance in a Spice subcircuit is defined as 1e-3 ohms!

Error found by WinSpice

If the simulation failure window appears with an error message, it may suggest a line in 5Spice’s circuit transfer file that has an error. Find the file (Xfer1.cir or Xfer2.cir) in 5Spice/WinSpice and find the indicated line number in the file. The subcircuit lines you see are copied from the subcircuit file, sometimes with the syntax translated. Now open the subcircuit file, find the matching line there and fix the error in the subcircuit file.

Also open the WinSpice program by clicking on its button on Windows’ bottom toolbar and check if there were multiple error messages. There are so many possibilities with untested subcircuits that 5Spice may not report them all.

As you modify and save the subcircuit file, you do not need to rebuild the Library unless you modify the .subckt line. You do need to double click the subcircuit symbol in the schematic and then click the OK button. This loads the modified version of the file into the program.

# CD4046 SPICE model

.subckt CD4046 sigin phcmpii phcmpi phpls compin vcoin
+              r1 r2 ce1 ce2 vcoout demout inhibit zener vdd vss
+                   OPTIONAL: DPWR=\$G_DPWR DGND=\$G_DGND
+                   PARAMS: MNTYMXDLY=0 IO_LEVEL=0
+                   Rin=1Meg S1=1  S2=0.5 M1=0.5 M2=1.0 Vx=10
+                   Kb=1 Vfree=0.0 Kc=-0.1 Vt=1.2 Vxqr=10

* Rin  = VCO Input Resistace
* S1   = Voltage Limiter linear slope
* S2   = Voltage Limiter non-linear slope
* Vx   = Input threshold voltage (between S1 and S2)
* Kb   = Arbitrary constant to adjust the value of the conversion gain (transimpedance gain)
* Vfree= Frequency dependent constant in Emult
* Kc   = Negative inverse amplitude of the square wave
* Vt   = Trigger voltage of Schmitt trigger (not used)
* Vxqr = Amplitude of square wave (not used)
* M1   = Current mirror multiplier to adjust oscillator frequency
* M2   = Current mirror multiplier to adjust oscillator frequency

* Preliminary model still under development based on Natinal Semiconductor CD4046BM
* RAPerez 9/98

* Phase detector section

U1 INVA(4) DPWR DGND sigin compin isigin icompin
+                    isigin icompin clk1 clk2
+ INVA_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL INVA_TIMING UGATE

U2 XOR DPWR DGND isigin icompin xorout
+ XOR_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL XOR_TIMING UGATE
***tplhty=20n tphlty=20n

U3 NAND(2) DPWR DGND q1 q2 pclr
+ NAND_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL NAND_TIMING UGATE (tplhty=1n tphlty=1n)

U4 DFF(1) DPWR DGND \$D_HI clr clk1 \$D_HI q1 qb1
+ DFF1_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL DFF1_TIMING UEFF tppcqlhty=4n tppcqhlty=4n tpclkqlhty=4n tpclkqhlty=4n

U5 DFF(1) DPWR DGND \$D_HI clr clk2 \$D_HI q2 qb2
+ DFF2_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL DFF2_TIMING UEFF tppcqlhty=5n tppcqhlty=5n tpclkqlhty=5n tpclkqhlty=5n

U7 BUFA(2) DPWR DGND fq1 fq2 s1 s2
+ BUFA_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL BUFA_TIMING UGATE

ST2 vdd phcmpii s1 0 swt
SB2 phcmpii vss s2 0 swt

.model swt VSWITCH (ROFF=2G RON=10m VOFF=0.8 VON=3.0)

U6 AND(2) DPWR DGND pclr reset clr
+ AND_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL AND_TIMING UGATE

Ureset STIM(1,1) DPWR DGND
+ reset
+ IO_HCT
+   +0s 0
+   2ns 1
+   1s 1

U8 NOR(2) DPWR DGND fq1 fq2 norout
+ NOR_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL NOR_TIMING UGATE

U9 ANDA(2,2) DPWR DGND q1 od1 q2 od2 fq1 fq2
+ ANDA_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL ANDA_TIMING UGATE

U10 DLYLINE DPWR DGND q1 od1
+ DLY_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U11 DLYLINE DPWR DGND q2 od2
+ DLY_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL DLY_TIMING UDLY dlyty=12n

U12 BUFA(3) DPWR DGND norout xorout vcosqr phpls phcmpi vcoout
+ BUFB_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL BUFB_TIMING UGATE

* VCO Section

Rin vcoin vss {Rin}
Evlim vlim 0 value={if(v(vcoin,vss)<v(vdd,vss),
+                   S1*v(vcoin,vss),S2*(v(vcoin,vss)-v(vdd,vss))+v(vdd,vss))}
Rvlim vlim 0 1Meg
Emult mix 0 value={v(vlim)*Kb+Vfree}
*Hmult mix 0 poly(1) Vcm 1.44 0.586
Rmult mix 0 1

Edemout demout 0 table={ 200Meg*v(vcoin,demout)*v(off) } (-20,-20) (20,20)
Rdemout demout 0 1Meg
ER2 ir2 0 vdd ir2 200Meg
VR2 ir2 r2
ER1 ir1 0 mix ir1 200Meg
VR1 ir1 r1
+ (0.5,1.43) (1,1.6) (10,1.04) (50,0.67) (100,0.84) (101,1)
+ (102,1) (1000,1)
*GIM ce1 0 value={(M1*I(VR1)+M2*I(VR2))*Kc*V(sqrrc)}
*GIM ce1 0 value={(24*I(VR1)+3.067*I(VR2))}
Vcext ce2 0
Cstray ce1 ce2 6p
Rcext ce1 ce2 1T
Etrngl trngl 0 ce1 0 1
Rtrngl trngl 0 1Meg

Esqr sqr 0 value={-10Meg*V(trngl)+1.2Meg*V(sqrrc)}

Rsqr sqr sqrrc 0.1T
Csqr sqrrc 0 10f
Dsqr1 sqrrc 13 Diode
Vsqr1 13 0 {Vx}
Dsqr2 14 sqrrc Diode
.model Diode D (IS=10u N=0.1 CJO=80f RS=1m)
*.model Diode D (IS=10u N=0.001 CJO=80f)
Vsqr2 14 0 {-Vx}
Ipls 0 sqrrc pwl 0 0 10n 0 20n 0.01u 0.1u 0.01u 0.12u 0 1 0
Evcoout vcosqr 0 table={5.0*v(off)*(v(sqrrc)/Vx)} (0.1,0.1) (4.5,4.5)
*Rvcoout vcosqr vcosqr1 1

**Et 7 0 TABLE {-10k*V(trngl)+1.2k*V(sqrrc)} (-2,-10) (2,10)
*Ipls 0 sqrrc pwl 0 0 10n 0 20n 1u 0.1u 1u 0.12u 0 1 0
*Et 7 0 value={table({-10Meg*V(trngl)+1.2Meg*V(sqrrc)},-10,{-Vx},10,{Vx})}
*Ro 7 sqrrc 100
*Co sqrrc 0 100p

*Est sqrrc o VALUE={table({2000k*(V(st)-V(trngl))},-2,{-Vx},2,{Vx})}
*Rst1 sqrrc st 8.8k
*Rst2 st 0 1.2k
*Cst st 0 200p ic=-10

Rinhbt inhibit 0 1Meg
Eoff off 0 value={if(v(inhibit)<0.9,1.0,0.0)}
Roff off 0 1Meg

Dzener vss zener znr
Rzener vss zener 1G
.model znr D(Is=1.004f Rs=.5875 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=160p M=.5484
+  Vj=.75 Fc=.5 Isr=1.8n Nr=2 Bv=5.2 Ibv=27.721m Nbv=1.1779
+  Ibvl=1.1646m Nbvl=21.894 Tbv1=176.47u)

.ends

# Arduino Simulation Projects using Arduino Simulation Library Models.

We have already seen in the article “ARDUINO Simulation PCB and 3D Models Libraries for Proteus”,  how to add the ARDUINO simulation, footprints and 3D models libraries to Proteus. Now we are going to see how is simple to use this components models for simulating ARDUINO projects. We can download for example the controlling LED project implemented with a microcontroler:

Fig. 1 Simple project implemented with a microcontroller model

We can replace the microcontroller, capacitors and crystal oscillator with the ARDUINO UNO simulation model:

Fig. 2 The same project above implemented with ARDUINO UNO simulation model

Let ‘s note that the PB5 output has a different numeration in the two models, but the .hex file should work for both, and also for the project implemented with ARDUINO Pro Mini model.

Click the right mouse button, over the model, and choose “Edit Properties”:

Fig. 3 Edit Properties

Load the hex file of the blink project in the “Program File” edit field:

Fig. 4 Load the Hex file

finally, let ‘s run the simulation:

Fig. 5 Run th simulation

Regarding the PCB assignment, let ‘s note that the only component that hasn ‘t an assigned footprint is the animated red LED:

Fig. 6 PCB package not specified for the LED component

We have to assign one to it: select the component, right mouse button, and let ‘s choose “Make Device”:

Fig. 7 Make Device window

Fig. 8 Click on “Add/Edit” button

It ‘s shown the “Package Device” window:

Fig. 9 Package Device window

Click on “Add” button and type the keyword “led” on the “Pick Packages” window, and select LED PACKAGE

Fig. 10 Type “led” on Pick Packages window

Double click over the first line, under the letter “A”

Fig. 11 Double click

and click on the anode pin of the PCB:

Fig. 12 Click on Anode pin

Same procedure for the other pin:

Fig. 13 Click on Cathode pin

Now, let ‘s click on the “Assign Packages” button,

Fig. 14 Packagings window shows the PCB assigned

Next button, select PACKAGE from the Component Properties and Definitions options:

Fig. 15 Select PACKAGE

Leave blank the Datasheet Filename edit field:

Fig. 16 leave blank the datasheet field

Choose USERDVC library, for example:

Fig. 17 choose USERDVC library

Confirm the update request in the next message box

Fig. 18 Update message box

# ARDUINO Simulation PCB and 3D Models Libraries for Proteus.

Arduino is an hardware/software open-source microcontroller board. It has been widely accepted in the hobbistic, educational and professional communities due to its versatility, ease of use and programming. This tutorial explains step by step how to simulate, visualize the layouts and 3D models of ARDUINO UNO, ARDUINO MEGA, and ARDUINO Pro mini boards in Proteus.

# SPICE simulation with Proteus of a Coils Tester.

Ing. Cristoforo Baldoni

This article deals with the Proteus simulation (version 7 and higher) of a low cost and very useful coils tester, easy to build by yourself. It ‘s the In-circuit LOPT (Line OutPut Transformer) Tester by Bob Parker that allows to evaluate the smooth functioning of a coil by turning on a number of different colored LEDs. It doesn ‘t measure the inductance value of a coil, but rather the ratio of its resistive part and the inductive part. This tester is very useful in finding coils with shorted turns, and wound components like yoke windings and SMPS transformers. Low loss components, will turn on four or more LEDs, while components with short circuits will turn on few or no LEDs. We ‘ll se how to implement and simulate with Proteus the circuit which consists of three sections: the low frequency pulse generator, the ring amplitude comparator and the LED bargraph display. We ‘ll se how to model a coil and try different values for the inductive and resistive component to validate the simulation. The Proteus simulation files of the device are available for download after accessing this article.

# Circuit-Breaker Model for Over-Current Protection Simulation of DC Distribution Systems.

T. ROBBINS
TELSTRA RESEARCH LABORATORIES
BOX 249 ROSEBANK MDC, CLAYTON VICTORIA 3168, AUSTRALIA
Email: t.robbins@trl.oz.au

Abstract: This article describes an electrical model of a thermalmagnetic circuit-breaker that can accurately simulate characteristic behaviour over a wide range of overcurrents, including operation in the magnetic region. The model has been validated against measured waveforms from both a high-current DC test facility and a distributed power system rack. The circuit-breaker model can be coupled with other distribution component models to simulate the protection performance in telecommunications DC distribution systems.

1.Introduction

The design and analysis of over-current protection for telecommunication DC power systems can be greatly assisted by the use of a computer-aided simulation tool. However, a simulation is only as accurate as the component models and element values used to represent the real world. This article reports on the development of a circuit-breaker model that can accurately represent circuit-breaker behaviour over a wide range of overcurrents.

The performance of protection, distribution and storage devices significantly affects both the reliability and safety of the DC power system. Voltage excursions caused by an over-current instance can cause electronic equipment to malfunction due to over-voltage, and disrupt service due to under-voltage. Poor discrimination between protection devices can cause upstream device operation, resulting in major interruption to service. The rapid advancement of both computing power and analogue circuit simulation programs derived from SPICE software provides a relatively user-friendly environment for over-current protection design and analysis. This is advantageous as telecommunications power distribution systems are often large and complex, and developing an equivalent circuit model for a power system is not a trivial task.

The circuit-breaker model described in this article implements the enhanced modelling functions available with PSpice’s Analog Behavioural Modelling to include circuit-breaker current, time and arcing dependent characteristics. This model complements and extends previously published modelling work [1-2] by Telstra Research Laboratories on other power system components.

2.Circuit-Breaker Characteristic Operation

A typical thermal-magnetic circuit-breaker operates (trips) in two distinct modes; the thermal mode occurs for device currents from 1 up to about 10-15 times the rated setting current, and the magnetic mode occurs for all current levels above the thermal operating region. Characteristic current-time curves for the device operating in the thermal region can be approximated by an equation where i n t equals a constant, whereas in the magnetic region the operating time (typically <20ms) is not well defined in device data curves and specifications, as test circuits are based on rectified AC power sources which have typical rise times exceeding a few milliseconds.

The circuit-breaker model presented in this paper has been developed for a 125A moulded device (10kA fault rating), which is commonly used to protect individual battery strings within Telstra’s distributed power supplies.

For device operation in the thermal region, the characteristic i n t form of the current-time curve can be obtained from the device specification curve as shown in Figure 1. A value of n = 3.5 gives an adequate fit over the range of currents within the thermal operating region.

Fig.1 125A circuit-breaker current-time operating
boundary curves (courtesy of GEC ALSTHOM
AUSTRALIA).

For device operation in the magnetic region, characteristic current-arc voltage-time behaviour has been observed for the circuit-breakers operating in a high-current DC test facility over a range of current levels and circuit time constants. At the start of such a fault instance, the current passing through the closed circuit-breaker contacts increases to a level where magnetic activation forces the contacts to open. As the contacts start to open an arc is developed which is inherently unstable and a complex voltage-current characteristic occurs as the arc progresses through to extinction.
For the 125A circuit-breaker operating in the magnetic region, the contacts are forced open when the current level typically rises above 2-4kA. Circuit-breaker operation was measured over a range of circuit conditions, such as:

· fast rates of current rise exceeding 10kA/ms, which resulted in short pre-arcing times of about 0.15- 0.2ms (eg. results from a test circuit with 5.4kA prospective current and 0.26ms time constant are shown in Figure 2).

· high prospective current levels exceeding 10kA, which result in pre-arcing times around 0.9ms for circuit time constants of about 1.2ms, as shown in Figure 3. It should be noted that special oscilloscope probing and current shunt techniques are required to record clean waveforms in the high transient noise environment that occurs in a high current test facility.

Fig.2 Measured current and voltage waveforms for
a 125A circuit-breaker operating in 54VDC test circuit
with 5.2kA prospective current and 0.25ms prospective
time constant; 1kA/div current, 20V/div voltage and
0.5ms/div.

Fig. 3 Measured current and voltage waveforms for
a 125A circuit-breaker operating in 54VDC test circuit
prospective time constant; 1kA/div current, 50V/div
voltage and 0.5ms/div.

# Fuse Model For Over-Current Protection Simulation of DC Distribution Systems.

T. Robbins
Telecom Australia Research Laboratories
Australia

Abstract: The design and analysis of over-current protection for telecommunication DC power systems can be greatly assisted by the use of a computer-aided simulation tool. This article reports on the development of a fuse model for SPICE derived software that can accurately represent characteristic fuse parameters. The fuse model can also be adapted to represent the operation of circuit breakers.

1.Introduction

The design and analysis of over-current protection for telecommunication DC power systems can be greatly assisted by the use of a computer-aided simulation tool. However, a simulation is only as accurate as the component models and element values used to represent the real world. This article reports on the development of a fuse model that can accurately represent fuse characteristics. The fuse model can also be adapted to represent the operation of circuit breakers.
The performance of over-current protection devices significantly affects both the reliability and safety of the DC power system. Voltage excursions resulting from the operation of a fuse during a short circuit can cause electronic equipment malfunction due to over-voltage, and disrupt service due to under-voltage. Poor discrimination between protection devices can cause upstream device operation, resulting in major interruption to service.

The rapid advancement of both computing power and analogue circuit simulation programs derived from SPICE software provide a user-friendly environment for over-current protection design and analysis. This environment is advantageous as telecommunications power distribution systems are often large and complex, and developing an equivalent circuit model for apower system is not a trivial task.

The analysis of DC distribution systems using computer simulation has been shown to provide fair agreement between simulated and experimental results [1,2,3]. However, the fuse models developed have not been able to accurately represent fuse characteristics. Typical parameters for a fuse operating in a circuit with a given time constant and prospective current are rated current ir, peak current ip, pre-arcing time tp, arcing time ta, total operating time tt= tp + ta, pre-arcing i²t (i²t)p, arcing i²t (i²t)a and total operating i²t (i²t)t= (i²t)p + (i²t)a. Figure 1 illustrates some of these parameters. The prospective current for a circuit is the maximum current that would be reached if the fuse did not operate.

The i²t or current-squared time rating is a commonly used fuse characteristic when operating current levels are much higher that the rated fuse current ir. The circuit time constant defines the ratio L/R, where L and R are the effective circuit inductance and resistance components in series with the fuse and energy source.

Fig 1. Typycal fuse parameters

A fuse model is developed in Section 2 and model validation is undertaken in Section 3. Section 4 discusses the development of other DC power system component models for application to the analysis of over-current protection, and the paper is summarised in Section 5.

# Straightforward Method to Design and Simulate with SPICE the Loop Compensation Controller for All Switching Power Supplies.

Ing. Cristoforo Baldoni

In this article we ‘ll see how to find the output power stage transfer function H(s), called the Control-to-Output function,  of the most switching power supplies: BUCK, BOOST, BUCK-BOOST, HALF-BRIDGE, FULL BRIDGE, both in voltage mode control and current mode control. In spite of the complexity of the different types of power supplies that use one or more output feedback, the output power transfer function H(s), can be reduced to a few schematic categories of general validity. We’ ll see when it’s the case to consider the effects of the RHPZ, the Right Half Plane Zero, and what it means in practical terms.
Once the components for the specific power supply have been sized, we can estimate with good approximation the transfer function which describes mathematically the output power stage. As seen in the article about the determination of POLES and ZEROS by inspection,  we ‘ll identify immediately the POLES and ZEROS which characterize the different switching categories.
We ‘ll draw the Bode plots of these functions with PSpice, and, according to their characteristics, we ‘ll choose the most suitable compensator G(s), implementing the compensation network with the operational amplifiers embedded in the microcontrollers. The SPICE simulation of the open loop transfer function G(s)*H(s), will allows us to evaluate the results for the system stability. Finally, we ‘ll apply this method in two real switching power supply: a low power flyback converter and an off-line, half-bridge switching.
This method allows us to speed up the design of the compensator G(s) in the prototyping phase before the physical measurement with the instrumentation.

It’s strongly recommended the reading of these articles:

-Forward function example

-Flyback function example

-Flyback function example with a Right Half Plane ZERO

-Origin POLE compensator

-Origin POLE Transfer function implementation

-Forward function compensated example

-One ZERO two POLES compensator

-One ZERO two POLES Transfer Function Implementation

-Flyback with RHPZ compensated

-Three POLES two ZEROS compensator

-Three POLES two ZEROS Transfer Function

-Transfer function of a real Flyback converter

-Compensator for the flyback converter

-Overall compensated  transfer function of the flyback converter

-Transfer function of a real Forward converter

-Compensator for the Forward converter

-Transfer function of compensator for the Forward converter

-Overall compensated  transfer function of the Forward converter

# SPICE simulation of a Combo Wave Generator.

In this article we ‘ll se how to implement a template for a Combination Wave Generator that can be a Surge Generator, a Line Impedance Stabilization Networks (LISN), motor control, ripple current, etc. This model can be very useful for hardware engineers which can utilize it in their projects to speed up project development. The platform used for the simulation is PSpice but
it can easily replicated in other SPICE simulation software.

The simplified model of the GPM consists of an High-Voltage source U, a charging resistor Rc, an energy storage capacitor Cc. This part of circuit is connected by a switch to 2 Pulse duration shaping resistors Rs, an impedance matching resistor Rm and a Rise time shaping indutor Lr, as in the picture below

typical values of this components are:  Cc=7.76μF,  Rs1=14.8 Ohm,  Rm=1.05 Ohm,  Lr=9.74μH,  Rs2=23.3 Ohm. The peak voltage on Rs2 can be 1KV, 2KV,..6KV.

In the following schematic we set the high voltage with the initial condition of the CapacitorCc, for example for 6KV, we set 6300 in the PSpice IC field of the Cc component. We can adjust the time in U1 to make surge hit at 90/270 degree or whatever phase we want.

Calibration of Surge Generator.

The IEC/EN 61000-4-5 standars requires the following waveform of open-circuit voltage with no Coupling/Decoupling network (CDN) connected

This is the result of the simulation that shows a voltage waveform that fullfills requirementof IEC/EN 61000-4-5

Below the image of the waveform of short-circuit current with no CDN connected

and here again the simulated results:

Ipeak is about 1.5KA, T1 is 8uS and T2 is 20uS. The effective coupling impedance is 2Ohm. The simulated current waveform fulfills requirement of IEC/EN 61000-4-5 standards.