D level-sensitive Latch in CMOS IC

SPICE simulation with LTspice of a D latch implemented with two cross-coupled CMOS inverters. When the clock signal is high, the output “follows” the input with a delay, When the clock goes low, the value of output Q cannot change until the clock goes back high again. Project Type: FreeComplexity: SimpleComponents number: 11-20SPICE software: LTspiceSoftware […]

Switching delays in a 3 input CMOS NAND

LTspice Parametric analysis of switching delays in a 3 input Nand gate with a load capacitance that varies from 0 to 100 femtoFarad. Project Type: FreeComplexity: SimpleComponents number:

3 inputs NOR gate with CMOS

LTspice simulation of a NOR static logic gate with 3 parallel NMOS and 3 series PMOS. The voltage switching point of NOR gate has a low value than ideal value of 2.5 Volt. Project Type: FreeComplexity: IntermediateComponents number:

3 inputs NAND gate with CMOS

LTspice siulation of a NAND static logic gate with 3 parallel PMOS and 3 series NMOS. Analysis of voltage transfer curve. Project Type: FreeComplexity: IntermediateComponents number:

Astable multivibrator with CD4011

SPICE simulation with LTspice of an Astable multivibrator with CD4011. Project Type: FreeComplexity: very-simpleComponents number:

Simple SPICE ESD Generator Circuit based on IEC61000-4-2 Standard

Università Politecnica delle Marche, Ancona, Italy. by Ing. Luca Buccolini A SIMPLE SPICE ESD GENERATOR CIRCUIT BASED ON IEC61000-4-2 STANDARD   WHAT IS ESD? Static charge is an unbalanced electrical charge at rest. Typically, it is created by insulator surfaces rubbing together or pulling apart. One surface gains electrons, while the other surface loses electrons. […]