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Digital Basic Components

SPICE projects of Half Adders, Full Adders, Comparators, Multiplexer, Demultiplexers, Decoders, Counters, Latches, Flip Flop, Registers, etc

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  • VCDL without distortion into the outputs

    Created by JacobBaker, published on 10-04-2013

    This modified version of Voltage-Controlled Delay Line regenerates full logic levels without introducing distortion into the signals. In this VCDL has been changed the last stage to two diff-amps with swapped input signals.The resulting signals have a width greater than the unmodified version. To get full logic levels, signals pass through inverters.

    FREE

    (only to registered users)

    Project Type: Free

    Complexity Spice Software Software Version Full version Components number
    Advanced LTspice IV No 51-100

    Path: SPICE Projects > General Electronics > Digital Basic Components

  • 8 stage Voltage-Controlled Delay Line

    Created by JacobBaker, published on 21-03-2013

    The VCDL is used to provide delay in a delay locked loop (DLL). This schematic has eight delay cells. the differential inputs were generated using an inverter and a transmission gate. the outputs are evenly spaced and they only swing up to Vref = 500mV. this is done to minimize the effects of power supply and ground noise on the delay of the circuit.

    FREE

    (only to registered users)

    Project Type: Free

    Complexity Spice Software Software Version Full version Components number
    Advanced LTspice IV No 51-100

    Path: SPICE Projects > General Electronics > Digital Basic Components

  • Delay-Locked Loop (DLL) SPICE simulation

    Created by JacobBaker, published on 15-03-2013

    Problems with PLL output jitter resulting from the VCO output frequency changing with a constant input voltage (VjnVC0 = constant) has led to the concept of a delay-locked loop (DLL). Assuming that a reference clock is available at exactly the correct frequency, the input data is delayed through a voltage-controlled delay line (VCDL) a time t0 until it is synchronized with the reference clock. Jitter is reduced by using an element, the VCDL, that does not generate a signal (like the VCO does). The transfer function Fclock/Fout is zero (the phase of the reference clock is taken as the reference for the other signals in the DLL, i.e., Fclock = 0), so that oscillator noise and the resulting jitter are not factors in DLL design.

    FREE

    (only to registered users)

    Project Type: Free

    Complexity Spice Software Software Version Full version Components number
    Intermediate LTspice IV No 11-20

    Path: SPICE Projects > General Electronics > Digital Basic Components

  • NRZ NonReturn to Zero Signal Generator

    Created by tobytone, published on 15-02-2013

    simple baseband unipolar, two level NRZ signal produced by a 7406 inverter. The format is the same as the TTL (transistor-transistor-logic) logic level 0 as as 0–0.8 V, and logic level 1 as 2–5 V, with output current less than 15 mA.

    FREE

    (only to registered users)

    Project Type: Free

    Complexity Spice Software Software Version Full version Components number
    Very Simple PSpice 9.1+ No <10

    Path: SPICE Projects > General Electronics > Digital Basic Components

  • Digital Clock without Microcontroller

    Created by Hobbyman, published on 06-12-2012

    Digital clock with hours/minutes/seconds setting buttons implemented with 74LS160 4-bit binary counters, 74LS21 dual 4-input AND gates, and CD4069 inverter circuits.

    FREE

    (only to registered users)

    Project Type: Free

    Complexity Spice Software Software Version Full version Components number
    Intermediate Proteus 7.6+ Yes 51-100

    Path: SPICE Projects > General Electronics > Digital Basic Components

  • DPLL with Phase Frequency Detector with Charge Pump Output

    Created by JacobBaker, published on 02-11-2012

    The CMOS implementation of a DPLL using the PFD with this configuration is preferred over the tri-state output, because of the better immunity to power supply variation. This simulation shows how too small values of the loop damping factor affects the loop, creating trouble locking.

    FREE

    (only to registered users)

    Project Type: Free

    Complexity Spice Software Software Version Full version Components number
    Advanced LTspice IV No 51-100

    Path: SPICE Projects > General Electronics > Digital Basic Components

  • PFD Phase Frequency Detector

    Created by JacobBaker, published on 23-10-2012

    This is a tri-state output circuit with outputs that can assume logic state '1', '0' and High impedance state, electrically isolated from the bus. This phase detector can be used in DPLL in place of XOR phase detector.It's implemented with inverters and nand gates. The SPICE circuit simulation shows that when the clock is lagging the data, the output of PFD is the up pulse indicating the dclock needs to speed up, when the data is lagging dclock the down pulse goes high indicating dclock should slow down.

    FREE

    (only to registered users)

    Project Type: Free

    Complexity Spice Software Software Version Full version Components number
    Advanced LTspice IV No >100

    Path: SPICE Projects > General Electronics > Digital Basic Components

  • DPLL with Active Proportional Integral Filter Loop

    Created by JacobBaker, published on 22-10-2012

    The Digital Phase Locked Loops with XOR Phase Detector shows a clock misalignment, the clock is not aligned to the middle of the data. To eliminate this misalignment called "static phase error" an active proportional integral loop filter is used.

    FREE

    (only to registered users)

    Project Type: Free

    Complexity Spice Software Software Version Full version Components number
    Advanced LTspice IV No >100

    Path: SPICE Projects > General Electronics > Digital Basic Components

  • DPLL Digital Phase Locked Loops with XOR Phase Detector

    Created by JacobBaker, published on 10-10-2012

    This is a fundamental circuit in the transmission of digital data. Before the transmission, data is loaded into a shift register and shifted out sequentially, using a system clock. At the receiving side, the receiver amplifies and eventually change the data back into digital logic levels. To shift the data back into a shift register, a clock signal is necessary. The DPLL generates a clock signal locked with the incoming signal, and clocks the shift register for recovering transmitted data.

    FREE

    (only to registered users)

    Project Type: Free

    Complexity Spice Software Software Version Full version Components number
    Advanced LTspice IV No >100

    Path: SPICE Projects > General Electronics > Digital Basic Components

  • Voltage Controlled Oscillator (VCO) for Digital Applications

    Created by JacobBaker, published on 01-09-2012

    the voltage controlled oscillator is an important component of a Digital Phase-Locked Loops (DPLL). If the output oscillation is not linearly related to the control voltage the non linear gain can reduce the quality of the performance of the DPLL. The output of the phase-locked loop can jitter or may not lock at all. Here a CMOS VCO with non linear gain and the linearized version.

    FREE

    (only to registered users)

    Project Type: Free

    Complexity Spice Software Software Version Full version Components number
    Intermediate LTspice IV No 51-100

    Path: SPICE Projects > General Electronics > Digital Basic Components

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