SR latch Asynchronous with NAND gates

(1 customer review)

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Description

SPICE simulation of a SR latch Asynchronous with NAND gates.

  • Free
  • Very simple
  • <10
  • PSpice
  • 9.1+
  • No
  • latch SR with NAND outputs

1 review for SR latch Asynchronous with NAND gates

  1. jmat977

    It should be noted that inputs are active low. Outputs are flipped (-Q should be Q and vice versa)

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